1. Field of the Invention
The present invention relates to a process for manufacturing a three dimensional IC device.
2. Description of the Related Art
In order to increase the degree of integration, various proposals for two dimensional IC (integrated circuit) devices have been made and utilized. As the two dimensional integration technique however has an eventual limitation with respect to the degree of integration, development of a technology for producing three dimensional devices has been considered and proposals have been made in relation to said technology. Nevertheless, the proposed three dimensional technologies thus far include those that can be utilized only in laboratories and those that can be utilized in IC manufacturing lines only to a very limited extent. Accordingly, commercial ICs are only two dimensional and further development of three dimensional IC technology is in great demand.
A three dimensional IC device in which a transistor integrated circuit is formed over an interlayer insulating layer, the interlayer insulating layer being formed on a transistor integrated circuit formed in a silicon substrate, was proposed so as to obtain a static random access memory (SRAM) having a large capacity and a low power consumption or other devices (see Y. Inoue et al, Symp. VLSI Tech., Tech. Dig., p.39, 1989 "4PMOS/2NMOS Vertically Stacked CMOS-SRAM with 0.6 .mu.m Design Rule"). In this proposal, a polysilicon layer is deposited over an interlayer insulating layer formed on a bulk, in which an integrated circuit is formed; the deposited polysilicon layer is then fused and recrystallized by an energy beam such as a laser beam; and, in this recrystallized silicon layer, transistors are formed to thus obtain a three dimensional integrated circuit.
This recrystallization process requires a long time, for example, about 3 hours when a wafer having a diameter of about 10 cm or 4 inches is entirely treated with an Ar laser; the crystallinity of the recrystallized layer is lowered as the number of laminated recrystallized layers increases, and the underlying integrated circuit device suffers deterioration of its characteristics from the heat required for the fusion and recrystallization of the overlaying layer.
There was also proposed a process for manufacturing a three dimensional integrated circuit device by bonding two semiconductor substrates having an integrated circuit formed therein; one of the two semiconductor substrates having a tungsten (W) bump, the other having an Au/In pool filled in a hole of a polyimide layer and the W bump and the Au/In pool being bonded with each other (see Y. Hayashi, "Evaluation of CUBIC (Cumulatively Bonded IC) Devices", 9th Symposium on Future Electron Devices, Nov. 14-15, 1990, pp 267-272). In this technique, the problems involved in the recrystallization process are removed, but the alignment, of the W bump with the Au/In pool, is made through an infra-red microscope that is not precise and makes the size of the Au/In pool as large as, for example, 8 .mu.m.times.8 .mu.m. Thus, the degree of integration suffers.
There is further proposed a process for manufacturing a three dimensional integrated circuit device, in which a second semiconductor substrate is bonded to a first semiconductor substrate through an insulating layer therebetween; the first semiconductor substrate having an integrated circuit and an alignment mark formed therein; and a second integrated circuit is then formed in the bonded second semiconductor substrate using said alignment mark of the first semiconductor substrate (see Japanese Unexamined Patent Publication (Kokai) No. 03-11658).
In this process, however, the alignment of the second semiconductor substrate with the first semiconductor substrate is made through a mechanical prealignment that is not precise and needs more than several tens m tolerance. Also, to expose the alignment mask after bonding the first to the second semiconductor substrates, an additional mask alignment step is required, which is disadvantageous from the viewpoint of not only accuracy but also process simplicity.
The object of the present invention is to provide a process for manufacturing a three dimensional integrated circuit device with a high degree of integration without deterioration of the crystallinity of the crystalline layer and the characteristics of the integrated circuit over a long period of time.